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Instruction set
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#	Item
171	Gregory Ichneumon Brown Web: www.gregorypbrown.com Phone: Add to Reading List Source URL: greg.ichneumon.net Language: English - Date: 2015-01-21 23:31:22 Computer architecture Computing Instruction set architectures Computer engineering Parallel computing Classes of computers Advanced RISC Computing MIPS instruction set System on a chip PowerPC Computer Multiprocessing
172	Automatic Instruction Set Extension and Utilization for Embedded Processors Armita Peymandoust, Laura Pozzi†, Paolo Ienne†, and Giovanni De Micheli † Computer Systems Laboratory Stanford University Add to Reading List Source URL: si2.epfl.ch Language: English - Date: 2005-05-20 05:53:16
173	Procedure Call Standard for the ARM Architecture Add to Reading List Source URL: infocenter.arm.com Language: English Subroutines Central processing unit Acorn Computers ARM architecture Calling convention Application binary interface Pointer 64-bit computing Processor register Stack SIMD Instruction set
174	2015 FormResearch Credit Add to Reading List Source URL: www.ftb.ca.gov Language: English - Date: 2016-01-27 12:49:17 Academia Taxation in the United States Academic transfer Course credit Education Limited liability company Instruction set Economy
175	Modular Deductive Verification of Multiprocessor Hardware Designs Muralidaran Vijayaraghavan1 , Adam Chlipala1 , Arvind1 , and Nirav Dave2 1 MIT {vmurali,adamc,arvind}@csail.mit.edu Add to Reading List Source URL: plv.csail.mit.edu Language: English - Date: 2015-12-16 11:34:18 Computing Computer architecture Computer hardware Microprocessors Central processing unit IBM PC compatibles Instruction set architectures Microcomputers Program counter X86
176	CITEd is pleased to announce a new set of Research in Brief articles on the use of multimedia materials for instruction, particularly for students with special needs. Please visit www.cited.org to read the full articles. Add to Reading List Source URL: www.cited.org Language: English - Date: 2007-09-18 12:37:14
177	Fast Binary Translation: Translation Efficiency and Runtime Efficiency Mathias Payer and Thomas R. Gross Department of Computer Science ETH Zürich Add to Reading List Source URL: hexhive.github.io Language: English - Date: 2016-06-13 11:08:40 Computer performance Software optimization Central processing unit Arrays Compiler optimizations Binary translation Lookup table Subroutine Instruction set Inline expansion Cache
178	Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator Zhenman Fang1,2 , Qinghao Min2 , Keyong Zhou2 , Yi Lu2 , Yibin Hu2 , Weihua Zhang2 , Haibo Chen3 , Jian Li4 , Binyu Zang2 1 The State Key Lab of ASIC & Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-08-23 22:17:16 Parallel computing Central processing unit Computer architecture Instruction set architectures Microprocessors CPU cache Computer architecture simulator ARM architecture Multi-core processor Speedup Emulator Microcode
179	The Newsletter of the Wakefield RISC OS Computer Club For all users of the Acorn and RISC OS family of computers Add to Reading List Source URL: www.wrocc.org.uk Language: English - Date: 2016-04-03 05:02:22 Computer architecture Software Computing Single-board computers Linux-based devices Microcontrollers ARM architecture Personal computers RISC OS Raspberry Pi RiscPC Reduced instruction set computing
180	Everybody be cool, this is a roppery! Vincenzo Iozzo zynamics GmbH Tim Kornau zynamics GmbH Add to Reading List Source URL: www.trailofbits.com Language: English - Date: 2016-04-15 11:36:17 Computing Computer architecture Computer engineering Central processing unit Return-oriented programming Instruction set Processor register Machine code Reduced instruction set computing Gadget Subroutine Stack machine

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